Miniaturized sensors & actuators such as micro-electromechanical sensors and integrated circuits (including gyros, accelerometers, GPS chip sets, micro-pumps, instrumentation amplifiers, photodetectors, microneedles, piezo-electric devices, cholesteric arrays, microcapacitive sensors, living tissue sensors, alterable form factor materials, and needle microarrays) are revolutionizing the ability to create devices for physiological, industrial, location and biometric monitoring and analysis. New low power RF interfaces are expanding the ability to track, monitor, report, interface or control with these sensors and actuators while new human interface devices are expanding the options for controlling the devices from wearable, physiological and neurological interfaces to smart sensing. In addition, new battery and energy generating technologies are also offering the promise of allowing these devices to be mounted in wearable form factors, on industrial or commercial equipment, and in remote locations due to the ability to harvest energy from the environment or operate from miniaturized batteries such as flexible paper batteries.
Although the aforementioned technologies show a lot of promise, the reality is that the distributed sensor, interface and communications revolution has been severely restricted in practice with devices created as prototypes with great fanfare that cannot be scaled with required functionality due to their high power requirements. The reason for the high power requirements is that in almost all cases the control and processing of sensor data must either be done locally with a microcontroller, digital signal processor (DSP) or field-programmable gate array (FPGA), or the raw data must be communicated to remote cloud or fixed equipment to do the real work of utilizing the data in real time.
Microcontrollers, processors, DSPs and FPGAs are components that utilize a lot of power because these components have to charge and discharge huge numbers of capacitive nodes millions or billions of times per second. Additionally, these components are usually programmed in high level languages such as C++ which increases the number of cycles required to perform mathematics or transformations. In general, the power required by leading microcontroller architectures is much too large to be utilized for significant localized processing with extremely small batteries if any operating lifetime is to be expected. The result has been that most sensors requiring significant filtering, extraction, analysis or data fusion either are prototypes demonstrated with large power sources with the future promise to be scaled, which never comes true, or a separate analysis engine is required increasing transmission requirements (as raw data must be sent) and making remote use of devices away from cellular or RF networks impossible for real time use.
A mathematical method used in digital form in microcontrollers, processor, DSPs and FPGA implementations of multi-sensor/actuator systems which have been utilized to a limited extent, primarily academically, are neural networks. Neural networks can efficiently synthesize any mathematical transfer function, and have shown unique capabilities for recognition and identification, classification, and control applications. Unfortunately, most implementations of neural networks are power hungry and slow as they have been implemented using digital means.
Analog neural networks have been shown to utilize a fraction of the current required by digitally implemented systems and are much faster due to the synchronous update of all the nodes rather than the sequential update of digital systems. Analog neural networks are often built using continuous analog multipliers. Continuous have generally been implemented as analog multipliers such as Gilbert multipliers, with extensions such as floating gate control of the multiplier inputs.
A good example of an emerging application are the personal fitness devices including bands and watches that are presently being introduced in the industry under the wearables banner. These devices do not generally have the ability to extract heart rate and higher order physiological information during motion due to the power that would be required for the analysis mathematics on digital processors or the power that would be required to transmit the raw information wirelessly to a device capable of such analysis in real time, assuming one were available. With the analog mathematical engine taught in this invention it is possible to process such information in real time due to the synchronous update capabilities of the analog neural network and at a reasonable power level due to the innovations taught herein.
While analog neural networks have many advantages, these networks still use too much power due to the continuous nature of the current connecting the neurons to produce the weightings. Additionally, analog neural networks are difficult to layout properly especially when dynamic connections are desired to modify the neural network configuration (such as number of neurons and number of layers, error propagation routine types, connections and biases). Furthermore, the current connections tend to be high impedance nodes which are susceptible to noise, glitching, leakage, and coupling problems which can reduce the effectiveness of the neural network and make layout risky and complex. Finally, floating gate technologies controlling the current into the multipliers limit the number of times the network can be modified since all floating gate technologies, whether tunneling or injected, have a limited number of write, clear and re-write cycles available. In fact, the learning processes and forward or back propagation error functions modify the charge on the floating gates so many times that the utilization of the flexible capabilities of the floating gate for multiple configurations is severely limited. Floating gate current sources which are an integral part of analog multipliers cannot be easily replaced with capacitive control with a write capability to the floating gate due to the difficulty in actively and accurately replicating the capacitive voltage to produce the required current in the multiplier, as well as the capacitive discharge characteristics over time, and as methods are attempted to do so, the additional circuitry designed to overcome offsets, leakages and temperature shifts degrade the quality of the neural network.
Switched capacitor circuits, including configurations such as switched capacitor gain circuits or cells, integrators, doublers, and filters have long been recognized as one of the best ways to implement high accuracy analog circuits without the silicon die area and inaccuracies that can result from relying on the absolute values of on-chip passive components such as resistors or capacitors. Switched capacitor circuits operate by controlling charge transfer between capacitors. Generally, charge is transferred between scaled capacitors with semiconductor switches that are switched at a frequency that effectively controls the rate of charge transfer, or current, in place of less accurate and much larger resistors that would otherwise be used. There is generally a setup or load phase or period during which inputs to the switched capacitor input capacitors are collected and then a charge transfer phase or period where the charge stored on the switched capacitor input capacitors is transferred to the output capacitors. In many switched capacitor circuits the output of the switched capacitor circuit is only accurate at the end of the charge transfer phase. Modifications to switched capacitor circuits include means to reduce or eliminate offset and noise by using additional capacitors which remove offsets or noise non-idealities using clever configurations which collect and then remove such non-idealities either during the setup or the charge transfer portion of operation. Additionally, there can be additional phases during switched capacitor circuit operation such as a period during which all switches are off or calibration phases which may happen continuously or periodically. Configurations including parasitic insensitive gain, integrator and doubler circuits as well as nulling and calibration techniques are known to those skilled in the art.
FIG. 1 is a schematic of a conventional switched capacitor inverting gain circuit 10. Operation of the switched capacitor inverting gain circuit 10 is as follows: i) With switch 1 and switch 3 closed capacitor C1 is charged to the input voltage Vin; ii) switch 1 and switch 3 open, and switch 2 and switch 4 close; iii) In order to maintain the same voltage at the inverting terminal (−) as the non-inverting terminal (+) of the operational amplifier (op amp) 12, the op amp 12 supplies a current I to produce a charge equal and opposite to the previously stored charge on C1 (Vin*C1), where the current I has to flow through C2, which then charges C2 to a voltage of −(C1/C2)*Vin, and produces that voltage on the output (Vout) at the end of the charge transfer period since the inverting terminal is held by the op amp 12 at ground.
FIG. 2 shows an alternate implementation of a conventional switched capacitor circuit 20. In FIG. 2, the op amp 12 of FIG. 1 is replaced by a current source 22 and a comparator 24. Activation of the switch 26 to voltage vp simply ensures that voltage vx is pulled below the reference voltage of the comparator during each cycle (ie., vp must be less than the reference, vcm or ground). The operation is similar to the previous example: i) switch 1 and switch 3 close charging C1 to Vin; ii) switch 1 and switch 3 open and switch 2 and switch 4 close; iii) with switch 2 and switch 4 closed the switch 26 turns on, then current source 22 (I1) is enabled, and then 26 turns off. In this case the current source 22 will supply a current the same way that the op amp 12 of FIG. 1 did. Except, in this case the comparator 24 detects that voltage vx has reached the reference (vcm or ground), and disables the current source 22 once voltage vx reaches the reference (vcm or ground). Thus at the end of the charging period, the nodes are at the same potential as they were in the op amp case of FIG. 1, but the complexity of the op amp, including its loop response, offset, current demand and other non-idealities are replaced with a simple open loop comparator 24 and current source 22 combination. The node vx will not reach ground until the charge previously stored on C1 (Vin*C1) is cancelled by exactly the same negative charge. The current which creates this charge must flow through C2 to reach C1 and therefore C2 will charge up to −(C1/C2)*Vin.
As shown in FIG. 2, the capacitor ratio (C1/C2) controls the voltage gain, and it is common to scale capacitors so as to control voltage according to the ratio of charge transfer (Q) in various switched capacitor circuits as Q=CV if capacitance C changes so will voltage V for a given charge Q). For example, in FIG. 3 the op amp and comparator/current source based switched capacitor circuits use unit capacitors which may be switched into and out of the circuit to control the voltage gain as described above. This type of circuit is commonly seen in data converters, filters, programmable gain circuits and other critical precision analog applications.
However, the reliance upon unit capacitors for matching or programmability requires careful attention to the capacitor layout and also requires a lot of silicon area. For example, dummy capacitors, routing, matching techniques, trim, and other measures are required to combat parasitics and the problems grow as the number of unit capacitors grows limiting the dynamic range of programmability. Unit capacitor matching often requires complex layout analysis and parasitic extract, and often re-spins of silicon. Furthermore, as additional switches and wires are utilized parasitic capacitances change causing errors in the circuit such as charge injection from mis-matched switches. In the op amp circuit of FIG. 1 it is not possible to scale the currents to the two capacitors (C1, C2). Also, as the input voltage must be fully loaded across C1, it is not possible to control the charge on C1 without complex voltage to current converters, which would degrade the accuracy of the switched capacitor circuits and make them undesirable for use.
The limitations of capacitor arrays to be utilized as weighted neurons with multiple inputs therefore limits the effective resolution of the weightings and summer functions to about five hits, and severely limits the capability of synthesizing transfer functions and functionality of the neural networks using capacitor arrays.
It would therefore be desirable to produce a switched capacitor circuit which may be dynamically scaled without having to rely on unit passives, such as unit capacitors, and the complexities of switching these capacitors into and out of circuit. It would be further desirable if the current provided, and thus the charge transferred could be controlled at a nodal level, such that selected capacitors within a switched capacitor circuit may see scaled currents, and the current rather than the capacitors could be scaled. As relative current accuracy is much easier to achieve using current mirrors than laying out switched capacitors arrays is, the result would therefore be more accurate in addition to simplifying the solution and saving silicon area.
Furthermore it is desirable to produce a neural network based upon neurons using a weighted input, summer, decision circuit methodology that is more power efficient than a continuous implementation, that is resilient to noise coupling, and allows modifications to enable re-configuration of the neural network without significant difficulty. Specifically, it would be desirable that the neural network may be trained by adjusting dynamic transconductors, and then once the error function is minimized the transconductor magnitudes may be connected to non-volatile storage, such as analog floating gate or digital eeprom or flash to remember desired weightings and biases, where the non-volatile memory or storage devices are limitedly used and not degraded during learning or multiple learning events.